Principal RTL Methodology Architect

Grow with us

About this opportunity: Principal RTL Methodology Architect opportunity. Location - Austin, Texas. This is not a remote work opportunity.

We are Ericsson Silicon — and we’re building the future of 5G from the transistor up. Our Silicon Engineering unit is at the bleeding edge of ASIC and FPGA development, targeting the most advanced technology nodes on the planet to power Ericsson’s next-generation 5G telecommunications portfolio. This isn’t just a job — it’s a chance to leave your fingerprints on silicon that connects the world. With a team packed with world-class engineers and virtually unlimited opportunities to grow, this is where elite talent comes to do the best work of their careers.

What you will do

We’re looking for a Principal RTL Methodology Architect — a rare breed of engineer who can think at the system level, execute at the RTL level, and lead at the organizational level. You’ll be the driving force behind scalable frontend design methodologies deployed across global engineering teams, raising the bar on RTL quality, reuse, and development velocity. You won’t just write the rules — you’ll build the infrastructure that enforces them. This role demands someone who thrives at the intersection of methodology leadership and hands‑on silicon execution — someone equally comfortable defining enterprise‑wide lint signoff frameworks as they are deep in microarchitecture development on critical silicon blocks. And if that weren’t enough? You’ll be on the frontier of AI‑driven silicon design, pioneering how machine intelligence transforms the way we build chips:

• AI‑accelerated RTL code generation and design productivity
• Intelligent linting and next‑gen static analysis
• AI‑optimized design space exploration and microarchitecture decisions
• Automated frontend design and verification workflows powered by ML

This is your opportunity to help redefine what silicon development looks like in the age of artificial intelligence.

Key Qualifications

• RTL Mastery — Deep, battle‑tested expertise in SystemVerilog/Verilog design, microarchitecture definition, and implementation for complex ASIC and SoC designs
• Architecture at Scale — Proven leadership defining and deploying enterprise‑scale RTL methodologies and frontend CAD architectures across global organizations
• Lint‑First Champion — Expert command of SpyGlass and Synopsys VC SpyGlass/VC Lint for rigorous RTL quality signoff
• Structural Validation Expert — Extensive knowledge of CDC analysis, static quality gates, and pre‑silicon design signoff frameworks
• IP Reuse Architect — Deep background building reusable RTL frameworks, standardized interfaces, and multi‑program reuse strategies that actually scale
• Low‑Power Guru — Hands‑on experience with UPF‑aware design, power domains, isolation, and retention strategies
• EDA Power User — Proficient across VCS, Xcelium, Questa, linting, CDC, and synthesis integration flows
• Automation Builder — Strong Python and scripting skills with real experience deploying CI/CD pipelines and design quality dashboards
• AI Visionary — Genuine passion for applying AI/ML to transform RTL productivity, intelligent static analysis, and next‑generation frontend automation

What You’ll Own

• Architect and deploy RTL design methodologies and frontend flows across IP, subsystem, and full SoC programs
• Define and enforce RTL quality signoff frameworks — lint, CDC, static analysis — baked directly into CI‑driven development pipelines
• Champion lint‑first design culture and establish standardized RTL coding guidelines and quality metrics that teams actually adopt
• Build and scale reusable IP platforms and configurable RTL frameworks powering efficient multi‑program silicon development
• Optimize frontend design flows integrating static analysis, simulation, and synthesis readiness at every stage
• Stay hands‑on — approximately 50% of your time contributing directly to microarchitecture development and critical silicon block implementation
• Deploy automation frameworks and CI/CD pipelines that measurably accelerate design productivity, regression efficiency, and quality tracking

Ready to shape the future of silicon? This is where methodology meets mastery — and where your work will power the networks of tomorrow.

Equality & Inclusion

Ericsson uses a merit‑based hiring approach that values people with different experiences, perspectives and skillsets. We truly believe this approach drives innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity employer.

Accommodations

If you need assistance or to request an accommodation due to a disability, please contact Ericsson at

Disclaimer

DISCLAIMER: The above statements are intended to describe the general nature and level of work being performed by employees in this position. They are not an exhaustive list of all responsibilities, duties and skills required for this position, and you may be required to perform additional job tasks as assigned.

Compensation and Benefits at Ericsson

Your Pay The salary range for this position is dependent on various factors including, but not limited to, location, and the candidate’s combination of job‑related knowledge, qualifications, skills, education, training, and experience.

Your Health Ericsson offers excellent health benefits including the choice of three medical plan options and a dental plan option that allow an employee to select the level of coverage that suits their needs. Employees will receive company credits in an amount equal to the cost that Ericsson pays toward the cost of their medical and dental premiums for themselves and eligible covered dependents.

Your Financial Security We invest in both your short and long‑term financial wellbeing. The Ericsson US 401(k) Plan offers an automatic 3% company contribution and Ericsson match $1 for every $1 you put into the 401(k) Plan on the first 3% of your eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay. When you contribute at least 5% of eligible pay, you are receiving Ericsson’s full matching contributions of 4%. Matching and company automatic contributions stop when your total eligible pay for the year reaches the IRS limits. Employees will also receive company credits in an amount equal to the cost of basic life insurance and basic accidental death and dismemberment coverage, as well as short‑term and long‑term disability coverage. Employees also have the option to participate in Ericsson’s Stock Purchase Plan.

Your Time Your work‑life balance is important to us. New employees are provided a minimum of 15 days of accrued vacation, up to 3 personal days per year, 11 annual holidays, 8 hours of volunteer time, and 80 hours of sick time annually. Please note paid time off is pro‑rated based on the employee’s start date. Furthermore, Ericsson provides up to 16 weeks of paid maternity leave and 6 weeks of parental or adoption leave at 100% of pay.

Additional Benefits Ericsson offers many other company‑paid benefits such as financial wellness programs, educational assistance, matching gifts, and recognition programs.

Location

Primary country and city: USA Austin, Texas

Job Details

Job details: Developer

Recruiter

Primary Recruiter: Jim Everett