Verification Engineer - SystemVerilog/UVM for Trading

IMC Trading is seeking a Verification Engineer to join its globally distributed R&D team in Chicago. You will verify complex hardware designs, develop testbenches, and automate flows to accelerate trading decisions to the technological limit.

You will collaborate with RTL and SW teams, use UVM, SystemVerilog/Verilog, and C++, and contribute to metrics-based verification. A discretionary bonus and comprehensive benefits are part of the package.